1. Field of the Invention
The present invention relates to a differential amplifier with an input auxiliary circuit and a shield circuit such that the range of an input common-mode voltage is extended and the operation speed is increased.
2. Description of Related Art
A differential amplifier is an essential unit in an electronic device for analog signal processing. In data transmission, differential amplifier is used for frond-end receiver to amplifying desired signals. Because most communication channels require higher operation speed and wider voltage range, the conventional differential amplifier has to be improved.
FIG. 1 is a diagram of a conventional differential amplifier. Referring to FIG. 1, in the conventional differential amplifier, a pair of N-type metal-oxide-semiconductor (NMOS) transistors (i.e., the NMOS transistors 100 and 102) is disposed as a pair of input transistors of the differential amplifier. A pair of gates of the NMOS transistors receives a pair of differential voltage signals, and a pair of sources thereof is connected to a system low voltage (for example, a ground voltage) through a current source 108.
The load of the differential amplifier is a pair of P-type MOS (PMOS) transistors (i.e., the PMOS transistors 104 and 106), and the PMOS transistors are diode-connected. The common-mode voltage of output terminals 110 and 112 in foregoing structure is determined by the voltage level of a system high voltage VDD. Namely, the output common-mode voltage is the system high voltage minus the VSG voltage of the PMOS transistors 104 and 106.
By using the diode-connected PMOS transistors as the load of a differential amplifier, the operation speed of the differential amplifier is limited. This is because when the input transistors of differential amplifier are completely switched, all the current in the current source 108 flows to one side of input transistors, and the current at the other side is zero. Accordingly, one side of the diode-connected PMOS transistors 104 (or 106) charges the corresponding output terminal. The charging current decreases as the output voltage increases due to the decrease of VSG voltage of the diode-connected PMOS transistors. Namely, the equivalent resistance of the diode-connected PMOS transistors increases with the increase of the output voltage (i.e., the RC time constant of the output terminal increases with time), so that the high voltage level of the output terminals cannot reach a stable state.
In other words, when the input differential signal is random data, the output high voltage level varies with the frequency of the input data pattern. As a result, the output signals generated by the differential amplifier will suffer from inter-symbol interference (ISI).
FIG. 2 is a diagram of a conventional differential amplifier. Referring to FIG. 2, this conventional differential amplifier adopts a similar design as the differential amplifier illustrated in FIG. 1 in order to achieve higher operation speed, wherein the NMOS transistors 100 and 102 are disposed as an input pair, and the load thereof is still implemented with the PMOS transistors 104 and 106. However, two impedance devices R1 and R2 are disposed for detecting the common-mode voltage of the output terminals, and the impedance devices R1 and R2 are connected to the gates of the PMOS transistors 104 and 106. In this structure, the output common-mode voltage is determined by the system high voltage VDD, and which is the system high voltage VDD minus the VSG voltage for the PMOS transistors 104 and 106.
The differential amplifier illustrated in FIG. 2 is more suitable to high-speed operation than the differential amplifier illustrated in FIG. 1. This is because the gates of the PMOS transistors 104 and 106 are common-mode terminals. Ideally, the output common-mode voltage does not change with the differential signals. Namely, the PMOS transistors 104 and 106 are not turned off during current switching, and ideally, a fixed voltage VSG and a fixed charging current are maintained. In addition, the equivalent differential resistance at the output terminals 110 and 112 is determined by the equivalent resistance of the impedance devices R1 and R2, and which does not change with the output voltage. Namely, a fixed RC time constant is kept at the output terminals. With sufficient circuit bandwidth, the level of the output voltage does not change with the frequency of the input data pattern. Accordingly, ISI will on be produced.
However, even though the circuit structure described above is suitable to high operation speed, the lowest input common-mode voltage is limited, wherein the lowest input common-mode voltage has to be higher than the voltage required by the current source 108 plus the VGS voltage of on the NMOS input transistors 102 and 104.
Thereby, the circuit structures of conventional differential amplifiers still need to be further improved to achieve a better performance.